IA82510_11 Datasheet, PDF (19/25 Pages) InnovASIC, Inc – Asynchronous Serial Controller

IA82510
Asynchronous Serial Controller
Data Sheet
February 25, 2011
Table 7. Summary of Errata (Continued)
Errata
No.
12
Problem
Device fails to reset interrupt signal in auto acknowledge mode
when character is read from RX FIFO.
13 RX FIFO locks up unexpectedly just after configuration and
before starting reception.
14 Unreliable transmits in AUTO TX mode.
Ver. 00 Ver. 01 Ver. 02
Exists Fixed Fixed
NA Exists Exists
NA Exists Exists
7.2 Detail
Errata No. 1
Problem: Scrambled data during boot code shuts down UART, however device works for
application code.
Description: The RX FIFO is locked, configuration of all registers is done, then the RX FIFO is
unlocked just before entering loopback mode in both boot and application code before normal
operations begin. Boot code additionally does a blind block read of all registers before normal
operations including two reads from the unwritten RX Data FIFO. RX unlock command is
inadvertently incrementing the write pointer. For boot code, the two reads of RX data cause the
read/write pointers to be permanently out of sync. For application code, the pointers end up
synched to the same location, only because the code waits for four characters before reading. This
ends up causing an RX overrun, but to our favor because the pointers are now synched.
Workaround: Execute a “Flush RX FIFO” command (via RCM register) after configuration and
block read is complete.
Errata No. 2
Problem: Device does not operate at 8 MHz in divide-by-one mode.
Description: System testing revealed this operational deficiency.
Workaround: Switch to divide-by-two mode using 2X clock input.
®
IA211001219-05
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 19 of 25
1-888-824-4184