IA82510_11 Datasheet, PDF (14/25 Pages) InnovASIC, Inc – Asynchronous Serial Controller

IA82510
Asynchronous Serial Controller
Data Sheet
February 25, 2011
Table 5. DC Parameters
Symbol
V_IL
V_IH1
V_IH2
V_OL
V_OH
I_LI
I_LO
I_CC
I_PU
I_STBY
I_OHR
I_OLR
C_IN
C_IO
C_XTAL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
I/O Capacitance
X1, X2 Load
Notes
(1)
(1)
(2)
(2),(8)
(3),(8)
(4)
(5)
(6)
(12)
(9)
(10)
(11)
(7)
(7)
Min
-0.5
2.1
2.1
2.4
-28.3
N/A
Max
0.3
V_DD+.3
V_DD+.3
0.4
1
10
1.12
-137
100
1.92
5
6
6
Unit
V
V
V
V
V
A
A
mA/MHz
A
A
mA
mA
pF
pF
pF
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @I_OL = 1.92 mA.
3. @I_OH = 1.92 mA.
4. 0< V_IN <V_CC.
5. 0.4V < V_OUT < V_CC – 0.4V.
6. V_DD = 5.5V, V_IL = 0.7V (max), V_IH = V_DD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X
CLK, I_OL = I_OH = 0.
7. Freq. = 1 MHz.
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output drive
requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured
to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW.
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ V_in = 0.0V, V_DD = 5.5V.
®
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