XC2238M Datasheet, PDF (90/102 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family Derivatives / Base Line

XC2238M, XC2239M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.5 Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 29 SSC Master/Slave Mode Timing for Upper Voltage Range
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Co
ndition
Master Mode Timing
Slave select output SELO active t₁ CC t_SYS –
1)
ns ²⁾
to first SCLKOUT transmit edge
-8
Slave select output SELO inactive t₂ CC t_SYS –
3)
ns
after last SCLKOUT receive edge
-6
Transmit data output valid time t₃ CC -6
–
9
ns
Receive data input setup time to t₄ SR 31
–
–
ns
SCLKOUT receive edge
Data input DX0 hold time from t₅ SR -4
–
–
ns
SCLKOUT receive edge
Slave Mode Timing
Select input DX2 setup to first t₁₀ SR 7
–
–
ns ⁴⁾
clock input DX1 transmit edge
Select input DX2 hold after last t₁₁ SR 7
–
–
ns ⁴⁾
clock input DX1 receive edge
Data input DX0 setup time to
t₁₂ SR 7
–
–
ns ⁴⁾
clock input DX1 receive edge
Data input DX0 hold time from t₁₃ SR 5
–
–
ns ⁴⁾
clock input DX1 receive edge
Data output DOUT valid time
t₁₄ CC 7
–
33
ns ⁴⁾
1) The maximum value further depends on the settings for the slave select output leading delay.
2) t_SYS = 1/f_SYS (= 12.5 ns @ 80 MHz)
3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock
output delay.
4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
90
V2.0, 2009-03