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XC2238M Datasheet, PDF (25/102 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family Derivatives / Base Line | |||
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XC2238M, XC2239M
XC2000 Family Derivatives / Base Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC223xM is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Table 6
XC223xM Memory Map
Address Area
Start Loc. End Loc.
IMB register space
FFâFF00H
Reserved (Access trap) F0â0000H
Reserved for EPSRAM E8â8000H
Emulated PSRAM
E8â0000H
Reserved for PSRAM E0â8000H
Program SRAM
E0â0000H
Reserved for Flash
CDâ0000H
Program Flash 3
CCâ0000H
Program Flash 2
C8â0000H
Program Flash 1
C4â0000H
Program Flash 0
C0â0000H
External memory area 40â0000H
Available Ext. IO area3) 21â0000H
FFâFFFFH
FFâFEFFH
EFâFFFFH
E8â7FFFH
E7âFFFFH
E0â7FFFH
DFâFFFFH
CCâFFFFH
CBâFFFFH
C7âFFFFH
C3âFFFFH
BFâFFFFH
3FâFFFFH
Area Size1) Notes
256 Bytes â
<1 Mbyte
Minus IMB registers
480 Kbytes Mirrors EPSRAM
32 Kbytes Flash timing
480 Kbytes Mirrors PSRAM
32 Kbytes Maximum speed
<1.25 Mbytes â
64 Kbytes â
256 Kbytes â
256 Kbytes â
256 Kbytes 2)
8 Mbytes
â
< 2 Mbytes Minus USIC/CAN
Data Sheet
25
V2.0, 2009-03
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