XC2238M Datasheet, PDF (26/102 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family Derivatives / Base Line

XC2238M, XC2239M
XC2000 Family Derivatives / Base Line
Functional Description
Table 6
XC223xM Memory Map (cont’d)
Address Area
Start Loc. End Loc. Area Size¹⁾ Notes
Reserved
MultiCAN/USIC regs.
20’C000_H 20’FFFF_H 16 Kbytes
20’8000_H 20’BFFF_H 16 Kbytes
–
Alternate location⁴⁾
Reserved
20’6000_H 20’7FFF_H 8 Kbytes
–
USIC registers
20’4000_H 20’5FFF_H 8 Kbytes
Accessed via EBC
MultiCAN registers
20’0000_H 20’3FFF_H 16 Kbytes Accessed via EBC
External memory area 01’0000_H 1F’FFFF_H < 2 Mbytes Minus segment 0
SFR area
00’FE00_H 00’FFFF_H 0.5 Kbyte
–
Dual-Port RAM
00’F600_H 00’FDFF_H 2 Kbytes
–
Reserved for DPRAM 00’F200_H 00’F5FF_H 1 Kbyte
–
ESFR area
00’F000_H 00’F1FF_H 0.5 Kbyte
–
XSFR area
00’E000_H 00’EFFF_H 4 Kbytes
–
Data SRAM
00’A000_H 00’DFFF_H 16 Kbytes –
Reserved for DSRAM 00’8000_H 00’9FFF_H 8 Kbytes
–
External memory area 00’0000_H 00’7FFF_H 32 Kbytes –
1) The areas marked with “<” are slightly smaller than indicated. See column “Notes”.
2) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000_H to C0’FFFF_H).
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
4) The alternate location for USIC and MultiCAN registers allows access to these modules using the same data
page pointer.
Up to 32 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A
section of the PSRAM with programmable size can be write-protected.
Note: The actual size of the PSRAM depends on the quoted device type.
16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.
The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for general purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
Data Sheet
26
V2.0, 2009-03