TLE8102SG_12 Datasheet, PDF (9/34 Pages) Infineon Technologies AG – Smart Dual Channel Powertrain Switch

TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5
Electrical and Functional Description of Blocks
5.1
Power Supply
The TLE8102SG is supplied by power supply line V_DD, used for the digital as well as the analog functions of the
device including the gate control of the power stages. A capacitor between pins V_DD to GND is recommended.
The TLE8102SG can be programmed via SPI to enter sleep mode. In sleep mode, all outputs are turned off and
all diagnosis and biasing circuits are disabled. These actions reduce the quiescent current consumption from the
power supply. However, the SPI configuration registers (except for the channel on/off register) are not reset when
the TLE8102SG enters sleep mode. To exit sleep mode, a wake up command must be sent via SPI.
Electrical Characteristics: Power Supply
V_DD = 4.5 V to 5.5 V, T_j = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter
Symbol
Limit Values
Min. Typ. Max.
5.1.1 Supply Voltage
V_DD
4.5
–
5.5
5.1.2 Supply Current
I_VDD
–
–
5
5.1.3 Supply Current in Sleep Mode
I_VDD(sleep) –
–
10
5.1.4 Wake up Time (after sleep mode)¹⁾ t_wake
–
–
100
1) Not subject to production test, specified by design.
Unit
V
mA
μA
μs
Conditions
–
–
–
–
5.2
Parallel Inputs
There are two input pins available on the TLE8102SG to control the output stages.
Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1 and IN2
controls OUT2. Please refer to Figure 5 for details. The input pins are active high and each have an integrated
pull-down current source. A comparator with hysteresis determines the state of the signal on INn. The zener diode
protects the input circuit against ESD pulses.
The BOL bit can be set via SPI. This bit determines if the output is exclusively controlled by the INn signals,
exclusively controlled by the corresponding data bits CHn_IN or by a Boolean OR or AND operation of the two
inputs. The default setting of the BOL bits programs the outputs to be controlled exclusively by the INn signals.
The SLEn bit can be set via SPI. This bit sets the slew rate of its assigned channel by selecting either slew rate 1
or slew rate 2. The slew rate also changes the over load switch off delay time (only for current limit 2).
IN1
I _{I N1}
IN
OR
&
SPI
C H 1_{I N}
BOL
chcahnannenl ^{e1l 2}
gate
control
SLE1
Figure 5 Input Control and Boolean Operator
Data Sheet
9
V1.5, 2012-08-17