TLE8102SG_12 Datasheet, PDF (10/34 Pages) Infineon Technologies AG – Smart Dual Channel Powertrain Switch

TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Electrical Characteristics: Parallel Inputs
V_DD = 4.5 V to 5.5 V, T_j = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter
Symbol
Limit Values
Min. Typ. Max.
5.2.1
5.2.2
5.2.3
5.2.4
Input Low Voltage
Input High Voltage
Input Voltage Hysteresis¹⁾
Input Pull-down Current
(IN1 to IN2)
V_INL
–
–
1.0
V_INH
2.0
–
–
V_INHys
100
200
400
I_{IN(1 … 2)} 20
50
100
1) Not subject to production test, specified by design.
Unit
V
V
mV
μA
Conditions
–
–
–
–
5.3
Power Outputs
5.3.1 Timing Diagrams
The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by
the CHn_IN bits of the serial peripheral interface SPI. The switching times t_ON and t_OFF are designed equally. The
switching time of each channel can be selected via SPI by programming the SLEn bit of the desired output. See
Figure 6 for details
CS
V_DS
80%
SPI: ON
t_ON
SPI: OFF
t_OFF
t
20%
t
Figure 6 Switching a Resistive Load
5.3.2 Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to V_DS(CL), as the inductance continues to drive
current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 7 for details.
The maximum allowed load inductance and current, however, are limited.
V _bat
V_DS(CL)
OUT
L,
R
I_D
L
V_DS
Figure 7 Inductive Output Clamp
Data Sheet
GND
10
V1.5, 2012-08-17