TLE42754_08 Datasheet, PDF (9/26 Pages) Infineon Technologies AG – Low Dropout Linear Fixed Voltage Regulator

TLE42754
General Product Characteristics
4.3
Thermal Resistance
Pos. Parameter
Symbol
Limit Value
Unit Conditions
Min. Typ. Max.
TLE42754D (PG-TO252-5)
4.3.4
4.3.5
4.3.6
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
3.7
–
27
–
110 –
K/W
K/W
K/W
–
2)
footprint only³⁾
4.3.7
–
57
–
K/W 300 mm² heatsink area
on PCB³⁾
4.3.8
–
42
–
K/W 600 mm² heatsink area
on PCB³⁾
TLE42754G (PG-TO263-5)
4.3.9
4.3.10
4.3.11
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
3.7
–
22
–
70
–
K/W
K/W
K/W
–
2)
footprint only³⁾
4.3.12
–
42
–
K/W 300 mm² heatsink area
on PCB³⁾
4.3.13
–
33
–
K/W 600 mm² heatsink area
on PCB³⁾
TLE42754E (PG-SSOP-14 exposed pad)
4.3.14
4.3.15
4.3.16
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
7
–
43
–
120 –
K/W
K/W
K/W
–
2)
footprint only³⁾
4.3.17
–
59
–
K/W 300 mm² heatsink area
on PCB³⁾
4.3.18
–
49
–
K/W 600 mm² heatsink area
on PCB³⁾
1) not subject to production test, specified by design
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
9
Rev. 1.1, 2008-09-24