ICE3RBR0665JZ Datasheet, PDF (9/31 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V

ICE3RBR0665JZ
Functional Description
controlled to 0.9mA by the Startup Cell. When the V_VCC
exceeds the on-threshold V_CCon=18V the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on, a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place
when V_VCC falls below 10.5V after normal operation
was entered. The maximum current consumption
before the controller is activated is about 150μA.
When V_VCC falls below the off-threshold V_CCoff=10.5V,
the bias circuit is switched off and the soft start counter
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero.
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 150μA.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 450μA.
3.3
Improved Current Mode
Soft-Start Comparator
FB
C8
0.67V
PWM OP
x3.3
Improved
Current Mode
PWM-Latch
RQ
Driver
SQ
CS
Figure 4 Current Mode
Current Mode means the duty cycle is controlled by the
slope of the primary current. This is done by comparing
the FB signal with the amplified current sense signal.
Amplified Current Signal
FB
0.67V
Driver
t
T_on
t
Figure 5 Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal the on-time T_on of the driver is finished by
resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
resistor R_Sense inserted in the source of the integrated
CoolMOS^®. By means of Current Mode regulation, the
secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external R_Sense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS^®.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by V_OSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted V_OSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing V_FB below that
threshold.
Version 2.0
9
7 Jun 2013