ICE3B0365J Datasheet, PDF (9/26 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOS™

CoolSET™-F3
ICE3Bxx65J
3.4
PWM Section
Oscillator
Duty
Cycle
max
Clock
Frequency
Jitter
Soft Start
Comparator
PWM
Comparator
Current
Limiting
0.75
PWM Section
FF1
1
S
Gate Driver
G8
RQ
&
G9
3.4.2
PWM-Latch FF1
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the internal CoolMOS™
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator or
the Current-Limit comparator. In case of resetting the
driver is shut down immediately.
3.4.3
Gate Driver
The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents.
The Gate Driver is active low at voltages below the
undervoltage lockout threshold V_VCCoff.
VCC
PWM-Latch
1
SoftS
Gate
Figure 6 PWM Section
3.4.1
Oscillator and Jittering
The oscillator generates a fixed frequency with
frequency jittering of ±4% from the fixed frequency
(which is ±2.7kHz from 67kHz) at a jittering period T_FJ.
The switching frequency is f_switch = 67kHz.
A resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D_max=0.75.
Once the Soft Start period is over and when the IC goes
into normal mode, the Soft Start capacitor will be
charged and discharged through internal current
source, I_FJ to generate a triangular waveform with a
jittering period T_FJ which is externally adjustable by the
Soft Start capacitor, C_SoftS (See Figure 4).
Gate Driver
Figure 7 Gate Driver
T_FJ = k_FJ * C_SoftS
where k_FJ is a constant = 4 ms/uF
eg. T_FJ = 4 ms if C_SoftS = 1uF
Gate
Depl. CoolMOS™
Version 2.3
9
8 May 2006