ICE3A1065LJ Datasheet, PDF (9/26 Pages) Infineon Technologies AG – Power Management Supply

CoolSET™-F3
ICE3A1065LJ
Functional Description
After the IC is switched on, the V_SoftS voltage is
controlled such that the voltage is increased step-
wisely (32 steps) with the increase of the counts. The
Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
decrease gradually and the duty ratio of the gate drive
increase gradually. The Soft Start will be finished in
20ms after the IC is switched on. At the end of the Soft
Start period, the current sink is switched off.
3.4
PWM Section
3.4.2
PWM-Latch FF1
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the internal
Depl. CoolMOS^TM. After the PWM-Latch is set, it is
reset by the PWM comparator, the Soft Start
comparator or the Current -Limit comparator. When it is
in reset mode, the output of the driver is shut down
immediately.
3.4.3
Gate Driver
0.75
Oscillator
Duty Cycle
max
Clock
Frequency
Jitter
PWM Section
VCC
PWM-Latch
1
Gate
Depl. CoolMOS™
Soft Start
Block
Soft Start
Comparator
PWM
Comparator
Current
Limiting
FF1
1
S
Gate Driver
G8
RQ
&
G9
Depl.
CoolMOS™
Gate
Gate Driver
Figure 8 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the internal
CoolMOS™ threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
Figure 7 PWM Section Block
3.4.1
Oscillator
The oscillator generates a fixed frequency of 100KHz
with frequency jittering of ±4% (which is ±4KHz) at a
jittering period of 4ms.
A capacitor, a current source and a current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D_max=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 100KHz ± 4KHz at period of 4ms.
(internal)
V_Gate
ca. t = 130ns
5V
t
Figure 9 Gate Rising Slope
Thus the leading switch on spike is minimized.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
Version 2.4
9
19 Nov 2012