ICE3A1065LJ Datasheet, PDF (10/26 Pages) Infineon Technologies AG – Power Management Supply

CoolSET™-F3
ICE3A1065LJ
Functional Description
During power up, when VCC is below the undervoltage
lockout threshold V_VCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.5
Current Limiting
PWM Latch Latched Off
FF1
Mode
Spike
Blanking
190ns
Current Limiting
1.66V
C11
Propagation-Delay
Compensation
activated, the current limiting is reduced to 0.31V. This
voltage level determines the maximum power level in
Active Burst Mode.
Furthermore, the comparator C11 is implemented to
detect dangerous current levels which could occur if
there is a short winding in the transformer or the
secondary diode is shorten. To ensure that there is no
accidentally entering of the Latched Mode by the
comparator C11, a 190ns spike blanking time is
integrated in the output path of comparator C11.
3.5.1
Leading Edge Blanking
V_Sense
V_csth
t_LEB = 220ns
V_csth
C10
Leading
Edge
PWM-OP
Blanking
220ns
&
G10
C12
0.31V
Active Burst
Mode
10k
1pF
D1
CS
t
Figure 11 Leading Edge Blanking
Whenever the internal Depl. CoolMOS™ is switched
on, a leading edge spike is generated due to the
primary-side capacitances and reverse recovery time
of the secondary-side rectifier. This spike can cause
the gate drive to switch off unintentionally. In order to
avoid a premature termination of the switching pulse,
this spike is blanked out with a time constant of t_LEB =
220ns.
Figure 10 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated Depl. CoolMOS™ is
sensed via an external sense resistor R_Sense. By means
of R_Sense the source current is transformed to a sense
voltage V_Sense which is fed into the pin CS. If the voltage
V_Sense exceeds the internal threshold voltage V_csth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
Depl. CoolMOS™ with very short propagation delay.
Thus the influence of the AC input voltage on the
maximum output power can be reduced to minimal.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
3.5.2 Propagation Delay Compensation
In case of overcurrent detection, there is always
propagation delay to switch off the internal Depl.
CoolMOS™. An overshoot of the peak current I_peak is
induced to the delay, which depends on the ratio of dI/
dt of the peak current (see Figure 12).
I_Sense
I_peak2
I_peak1
I_Limit
Signal2
I_Overshoot2
Signal1
t_{Propagation Delay}
I_Overshoot1
t
Figure 12 Current Limiting
Version 2.4
10
19 Nov 2012