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ICE2QS02G Datasheet, PDF (9/17 Pages) Infineon Technologies AG – Quasi-Resonant PWM Controller
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Quasi-Resonant PWM Controller
ICE2QS02G
Funtional Description
switching frequency from going lower than 20kHz,
otherwise which will cause audible noise in most cases.
3.3.2
Switch Off Determination
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor vCS is applied to an internal current
measurement unit, and its output voltage V1 is
compared with the regulation voltage VFB. Once the
voltage V1 exceeds the voltage VFB, the output flip-flop
is reset. As a result, the main power switch is switched
off. The relationship between the V1 and the vCS is
described by:
V1
=
3.3 ⋅ V + 0.7
CS
[3]
In addition, there is a maximum on time, tOnMax,
limitation implemented in the IC. Once the gate drive
has been in high state longer than the maximum on
time, it will be turned off to prevent the switching
frequency from going too low because of long on time.
3.4
Current Limitation
There is a cycle by cycle current limitation realized by
the current limit comparator to provide an overcurrent
detection. The source current of the MOSFET is
sensed via a sense resistor RCS. By means of RCS the
source current is transformed to a sense voltage VCS
which is fed into the pin CS. If the voltage VCS exceeds
an internal voltage limit, adjusted according to the
Mains voltage, the comparator immediately turns off
the gate drive.
To prevent the Current Limitation process from
distortions caused by leading edge spikes, a Leading
Edge Blanking time (tLEB) is integrated in the current
sensing path.
A further comparator is implemented to detect
dangerous current levels (VCSSW) which could occur if
one or more transformer windings are shorted or if the
secondary diode is shorted. To avoid an accidental
latch off, a spike blanking time of tCSSW is integrated in
the output path of the comparator .
3.4.1
Foldback Point Correction
When the main bus voltage increases, the switch on
time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant
primary current limit, the maximum possible output
power is increased, which the converter may have not
been designed to support.
To avoid such a situation, the internal foldback point
correction circuit varies the VCS voltage limit according
to the bus voltage. This means the VCS will be
decreased when the bus voltage increases. To keep a
constant maximum input power of the converter, the
required maximum VCS versus various input bus
voltage can be calculated, which is shown in Figure 5.
1
0.9
0.8
0.7
0.6
80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
Vin(V)
Figure 5 Variation of the VCS limit voltage according
to the IZC current
According to the typical application circuit, when
MOSFET is turned on, a negative voltage proportional
to bus voltage will be coupled to auxiliary winding.
Inside ICE2QS02G, an internal circuit will clamp the
voltage on ZC pin to nearly 0V. As a result, the current
flowing out from ZC pin can be calculated as
IZC
=
V-----B-----U----S----N-----a-
RZC1NP
[4]
When this current is higher than IZC_1, the amount of
current exceeding this threshold is used to generate an
offset to decrease the maximum limit on VCS. Since the
ideal curve shown in Figure 5 is a nonlinear one, a
digital block in ICE2QS02G is implemented to get a
better control of maximum output power. Additional
advantage to use digital circuit is the production
tolerance is smaller compared to analog solutions. The
typical maximum limit on VCS versus the ZC current is
shown in Figure 6.
1
0.9
0.8
0.7
0.6
300
500
700
900 1100 1300 1500 1700 1900 2100
Iz c(uA)
Figure 6
VCS-max versus IZC
Version 2.0
9
13 June 2008
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