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ICE2QS02G Datasheet, PDF (7/17 Pages) Infineon Technologies AG – Quasi-Resonant PWM Controller
Quasi-Resonant PWM Controller
ICE2QS02G
Funtional Description
3 Funtional Description
All values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1
General
switch-on and switch-off time points are each
determined by the digital circuit and the analog circuit,
respectively. As input information for the switch-on
determination, the zero-crossing input signal and the
value of the up/down counter are needed, while the
feedback signal VFB and the current sensing signal VCS
are necessary for the switch-off determination. Details
about the full operation of the PWM controller in normal
operation are illustrated in the following paragraphs.
ICE2QS02G is a second generation quasi-resonant
controller IC developed by Infineon Technologies. Its
application is mainly focused on power systems with
external standby power control, such as in LCD TV or
printer applications. Hence, the required IC VCC
voltage for the IC is here drawn from an auxiliary power
supply.
The digital frequency reduction system implemented in
this IC allows highly efficient power converter
throughout all the load range. This IC possesses also
numerous adjustable protection features, in order to
protect the system and customize the IC for the target
applications.
3.2
Startup Phase
At the time ton, the IC begins to operate with a soft-
start.By this soft-start the switching stresses for the
switch, diode and transformer are minimised. The soft-
start implemented in ICE2QS02G is a digital time-
based function. The preset soft-start time is 16ms with
4 steps. The internal reference for the feedback voltage
begins at 1.8V and with an increment of 0.55V for each
following step. During soft start, the Over Load
Protection function is disabled.
Vsst (V)
4.00
3.45
2.9
3.3.1
Digital Frequency Reduction
As mentioned above, the digital signal processing
circuit consists of an up/down counter, a ZC counter
and a comparator. These three parts are key to
implement digital frequency reduction with decreasing
load. In addition, a ringing suppression time controller
is implemented to avoid mistriggering by the high
frequency oscillation, when the output voltage is very
low under conditions such as soft start or output short
circuit . Functionality of these parts is described as in
the following.
3.3.1.1 Up/down counter
The up/down counter stores the number of the zero
crossing to be ignored before the main power switch is
switched on after demagnetisation of the transformer.
This value is fixed according to the feedback voltage,
VFB, which contains information about the output
power. Indeed, in a typical peak current mode control,
a high output power results in a high feedback voltage,
and a low output power leads to a low regulation
voltage. Hence, according to VFB, the value in the up/
down counter is changed to vary the power MOSFET
off-time according to the output power. In the following,
the variation of the up/down counter value according to
the feedback voltage is explained.
The feedback voltage VFB is internally compared with
three threshold voltages VFBZL, VFBZR1 and VFBZH, at
each clock period of 48ms. The up/down counter
counts then upward, keep unchanged or count
downward, as shown in Table 1.
2.35
Table 1 Operation of the up/down counter
1.8
ton
4
8
12
16 Time(ms)
Figure 3 Soft-start control voltage versus time
3.3
PWM Control
The PWM controller during normal operation consists
of a digital signal processing circuit including an up/
down counter, a zero-crossing counter (ZC counter)
and a comparator, and an analog circuit including a
current measurement unit and a comparator. The
vFB
Always lower than VFBZL
Once higher than VFBZL, but
always lower than VFBZH
Once higher than VFBZH, but
always lower than VFBZR1
Once higher than VFBZR1
up/down counter
action
Count upwards till
7
Stop counting, no
value changing
Count downwards
till 1
Set up/down
counter to 1
Version 2.0
7
13 June 2008