ICE1PCS01_07 Datasheet, PDF (9/18 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

CCM-PFC
ICE1PCS01/G
Functional Description
Full-wave
Rectifier
ISENSE
R2
I_INDUCTOR
R1
Current Limit
1.5V
1.43x
OP1
Deglitcher
C2
300ns _{Turn Off}
Driver
ICE1PCS01/G
Figure 9 Peak Current Limit (PCL)
3.4.4
Open Loop Protection / Input Under
Voltage Protect (OLP)
Whenever VSENSE voltage falls below 0.8V, or
equivalently V_OUT falls below 16% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V_IN for
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.8V as shown in the
IC block diagram in Figure 2.
3.4.5 Output Under Voltage Detection (OUV)
In the event of main interrupt or brown-out condition,
the PFC system is not able to deliver the rated output
power. This will cause the output voltage V_OUT to drop
below its rated value. The IC provides an output under
voltage detection that checks if V_OUT is falling below
50% of its rated value. Comparator C4 as shown in the
device block diagram (Figure 2) senses the voltage at
pin 6 (VSENSE) with a reference of 2.5V. If comparator
C4 trips, the IC will be shut down as in OLP. The IC will
be ready to restart if there is sufficient V_IN to pull V_OUT
out of OLP.
3.4.6 Over-Voltage Protection (OVP)
Whenever V_OUT exceeds the rated value by 5%, the
over-voltage protection OVP is active as shown in
Figure 7. This is implemented by sensing the voltage at
pin VSENSE with respect to a reference voltage of
5.25V. A VSENSE voltage higher than 5.25V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V_OUT.
3.5 Frequency Setting
The switching frequency of the PFC converter can be
set with an external resistor R5 at FREQ pin. The pin
voltage V_FREQ is typically 2.5V. The corresponding
capacitor for the oscillator is integrated in the device
and the R5/frequency relationship is given at the
“Electrical Characteristic” section. The
recommended operating frequency range is from
50kHz to 250kHz. As an example, a R5 of 33kΩ at pin
FREQ will set a switching frequency F_SW of 133kHz
typically.
3.6 Average Current Control
3.6.1 Complete Current Loop
The complete system current loop is shown in Figure
10.
From
Full-wave
Retifier
L1
R7
R2
R1
ISENSE
Current Loop
ICOMP
C3
Current Loop
Compensation
OTA2
1.1mS
+/-50uA (linear range)
S2
4V
Fault
ICE1PCS01/G
D1
R3 ^Vout
C2
R4
GATE
voltage
proportional to
averaged
Inductor current
PWM
Comparator
C1
Gate
Driver
RQ
S
PWM Logic
Nonlinear
Gain
Input From
Voltage Loop
Figure 10 Complete System Current Loop
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.6.2 Current Loop Compensation
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
10). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 5V in the event
of IC shuts down when OLP and UVLO occur.
3.6.3 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Version 1.2
9
06 Feb 2007