ICE1PCS01_07 Datasheet, PDF (10/18 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

CCM-PFC
ICE1PCS01/G
Functional Description
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D_OFF for a
CCM PFC system is given as
D_OFF
=
---V----^I--^N----
V_OUT
From the above equation, D_OFF is proportional to V_IN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D_OFF, and thus to the input voltage
V_IN. Figure 11 shows the scheme to achieve the
objective.
ramp profile
ave(I_IN) at ICOMP
3.6.4 Nonlinear Gain Block
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
3.7 PWM Logic
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T_OFFMIN,
are designed to meet a maximum duty cycle D_MAX of
95% at the GATE output under 133kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 13.
GATE
drive
t
Figure 11 Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T_OFFMIN (250ns typ.) and the ramp is
kept discharged. The ramp is then allowed to rise after
T_OFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D_OFF.
Figure 12 shows the timing diagrams of T_OFFMIN and the
PWM waveforms.
T_OFFMIN
250ns
PWM cycle
V_CREF(1)
V_RAMP
PWM
ramp
released
t
(1) _{VCREF is a function of VICOMP}
Figure 12 Ramp and PWM waveforms
Peak Current
Limit
Current Loop
PWM on signal
Toffmin
250ns
Current
Limit Latch
Q
S
L1
R
PWM on
Latch
S
L2 Q
R
G1
HIGH =
turn GATE on
Figure 13 PWM Logic
3.8 Voltage Loop
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V_OUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from V_OUT. The pin VSENSE is the input of
OTA1 which has an internal reference of 5V. Figure 14
shows the important blocks of this voltage loop.
3.8.1 Voltage Loop Compensation
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 14). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
Version 1.2
10
06 Feb 2007