HYS72D32000GR-7-B Datasheet, PDF (9/23 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
Input / Output voltage relative to V_SS
V_IN, V_OUT – 0.5
3.6
V
Power supply voltage on V_DD/V_DDQ to V_SS
V_DD, V_DDQ – 0.5
3.6
V
Storage temperature range
T_STG
-55
+150
o_C
Power dissipation (per SDRAM component)
P_D
–
1
W
Data out current (short circuit)
I_OS
–
50
mA
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Supply Voltage Levels
Parameter
Symbol
Limit Values
min.
nom.
max.
Device Supply Voltage
V_DD
2.3
2.5
Output Supply Voltage
V_DDQ
2.3
2.5
Input Reference Voltage
V_REF
0.49 x V_DDQ 0.5 x V_DDQ
Termination Voltage
V_TT
V_REF – 0.04 V_REF
EEPROM supply voltage
V_DDSPD
2.3
2.5
1 Under all conditions, V_DDQ must be less than or equal to V_DD
2 Peak to peak AC noise on V_REF may not exceed ± 2% V_{REF (DC)}.
V_REF is also expected to track noise variations in V_DDQ.
3 V_TT of the transmitting device must track V_REF of the receiving device.
2.7
2.7
0.51 x V_DDQ
V_REF + 0.04
3.6
Unit Notes
V
-
V
1)
V
2)
V
3)
V
DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS)
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
DC Input Logic High
V_{IH (DC)}
V_REF + 0.15
V_DDQ + 0.3
V
1)
DC Input Logic Low
V_{IL (DC)}
– 0.30
V_REF – 0.15
V
–
Input Leakage Current
I_IL
–5
5
µA
1)
Output Leakage Current
I_OL
–5
5
µA
2)
1) The relationship between the V_DDQ of the driving device and the V_REF of the receiving device is what
determines noise margins. However, in the case of V_{IH (max)} (input overdrive), it is the V_DDQ of the receiving
device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but
has no SSTL_2 outputs (such as a translator), and therefore no V_DDQ supply voltage connection, inputs must
tolerate input overdrive to 3.0 V (High corner V_DDQ + 300 mV).
2) For any pin under test input of 0 V ≤ V_IN ≤ V_DDQ + 0.3 V. Values are shown per DDR-SDRAM component.
INFINEON Technologies
9
2002-09-10 (revision 0.91)