HYS72D32000GR-7-B Datasheet, PDF (11/23 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100)
Symbol
Parameter/Condition
256MB
x72
1bank
-7
MAX
512MB
x72
1bank
-7
MAX
512MB
x72
2bank
-7
MAX
1GB
x72
2bank
-7
MAX
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK
IDD0 MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and 900
control inputs changing once every two clock cycles
1800 1395 2790
Unit ^Notes
5
mA 1, 4
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
990 1980 1485 2970 mA 1, 3, 4
Precharge Power-Down Standby Current: all banks idle; power-down
IDD2P
mode; CKE <= VIL MAX; tCK = tCK MIN
72
144 144 288 mA 2, 4
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE
IDD2F >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once 360 720 720 1440 mA 2, 4
per clock cycle, VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at 225 450 450 900 mA 2, 4
>= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
IDD3P
CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM.
162
324
324
648
mA 2, 4
Active Standby Current: one bank active; active / precharge;CS >= VIH
IDD3N
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs changing
495
once per clock cycle
IDD4R
Operating Current: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
1035
IDD4W
Operating Current: one bank active; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333; tCK = tCK MIN
1125
IDD5
IDD6
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
1620
27,0
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
2025
990
2070
2250
3240
54
4050
990
1530
1620
2115
54
2520
1980
3060
3240
4230
108
5040
mA 2, 4
mA 1, 3, 4
mA 1, 4
mA 1, 4
mA 2, 4
mA 1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
2 * n * IDDx[component] for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
11
2002-09-10 (revision 0.91)