HYS72D32000GR-7-B Datasheet, PDF (10/23 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
Symbol
Parameter/Condition
256MB 512MB 512MB 1GB
x72 x72 x72 x72
1bank 1bank 2bank 2bank Unit ^Notes
-8
-8
-8
-8
MAX MAX MAX MAX
5
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK =
IDD0 tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address 810 1620 1215 2430 mA 1, 4
and control inputs changing once every two clock cycles
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
900 1800 1305 2610 mA 1, 3, 4
Precharge Power-Down Standby Current: all banks idle; power-down
IDD2P
mode; CKE <= VIL MAX; tCK = tCK MIN
63
126 126 252 mA 2, 4
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
IDD2F
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
315 630 630 1260 mA 2, 4
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable 198
at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down
IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and 144
DM.
Active Standby Current: one bank active; active / precharge;CS >= VIH
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
IDD3N _{DQS inputs changing twice per clock cycle; address and control inputs}
405
changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
IDD4R _{outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,} 855
CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
Operating Current: one bank active; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
IDD4W _{outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A,} 945
CL=3 for DDR333; tCK = tCK MIN
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
1530
IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 27,0
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
1890
396
288
810
1710
1890
3060
54
3780
396
288
810
1260
1350
1935
54
2295
792
576
1620
2520
2700
3870
108
4590
mA 2, 4
mA 2, 4
mA 2, 4
mA 1, 3, 4
mA 1, 4
mA 1, 4
mA 2, 4
mA 1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
2 * n * IDDx[component] for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
10
2002-09-10 (revision 0.91)