1ED020I12FTA Datasheet, PDF (9/27 Pages) Infineon Technologies AG – Single IGBT Driver IC

EICEDRIVER®
1ED020I12FTA
Functional Description
2.3
Non-Inverting and Inverting Inputs
There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while
IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input pulse
width is defined to filter occasional glitches.
2.4
Driver Output
The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control
of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to
the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor.
Furthermore, it reduces the power to be dissipated by the driver.
2.5
Two-Level Turn-Off
The Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and OFF-
level. This additional level ensures lower V_CE overshoots at turn off by reducing gate emitter voltage of the IGBT
at short circuits or over current events. The V_GE level is adjusting the current of the IGBT at the end two level turn
off interval, therequired timing is depending on stray inductance and over current at beginning of two level turn off
interval.
Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the
required Zener diode connected between pin TLSET and GND2. The hold up time is set by the capacitor
connected to the same pin TLSET and GND2.
The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including
capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is given
the IC starts to discharge C_TLSET. Discharging C_TLSET is stopped after 500nsec. Then Ctlset is charged with an
internal charge current Itlset. When the voltage of the capacitor Ctlset exceeds 7V a second current source starts
charging Ctlset up to V_ZDIODE. At the end of this discharge-charge cycle the gate driver is switched on.
The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200ns) and
switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time T_TLSET during
switch-off. Due to digitalization the tpdon time can vary in time steps of 50nsec.
If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal
propagation delay of approximately 200ns and V_OUT begins to decrease. For switch off initiated by DESAT, the
gate driver switch off is delayed by desaturation sense to OUT delay. The output voltage V_OUT is sensed and
compared with the Zener voltage V_ZDIODE. When V_OUT falls below the reference voltage V_ZDIODE of the Zener diode
the switch off process is interrupted and Vout is adjusted to V_ZDIODE. OUT is switched to VEE2 after the hold up
time has passed.
The Two-Level Turn-OFF function can not be disabled.
2.6
Minimal On Time / Off Time
The 1ED020I12FTA driver requires minimal on and off time for propper operation in the application. Minimal on
time must be greater than the adjustable two level plateau time T_TLSET, shorter on times will be surpressed by
generating of the plateau time. Due to the short on time, the voltage at TLSET pin does not reach the comparator
threshold, therefore the driver do not turn on. A similar principle takes place for off time. Minimal off time must be
greater than T_TLSET, shorter off times will be surpressed, which means OUT stays on. A two level turn off plateau
can not be shortened by the driver. If the driver has entered the turn off sequence it can not switch off due to the
fact, that the driver has already entered the shut off mode. But if the driver input signal is turned on again, it will
leave the lower level after T_TLSET time by switching OUT to high.
Preliminary Datasheet
7
Version 1.2, 2010-05-21