PSB21391 Datasheet, PDF (85/253 Pages) Infineon Technologies AG – Siemens Codec with UPNTransceiver

PSB 21391
PSB 21393
Interfaces
2.3.5.1.5 Reset
RES
A low signal on the RST pin or setting the RES_TR bit in the SRES register to
’1’ resets also the layer-1 statemachine. The reset signals should be applied
for a minimum of 2 DCL clock cycles. The function of these reset events is
identical to the C/I code RES concerning the state machine.
2.3.5.1.6 C/I Indications
Indication (Downstream) Abbr. Code Remarks
Deactivation Request
DR 0000
Power-Up
PU 0111
Test Mode Acknowledge TMA 0010 Acknowledge for both SSP and SCP
Resynchronization
RSY 0100 Receiver not synchronous
Activation Request
AR 1000 Receiver synchronized
Activation Request Loop 3 ARL 1001 Local loop synchronized
Activation Request Loop 2 ARL2 1010 Remote loop synchronized
Activation Indication
AI 1100
Activation Indication Loop 3 AIL 1101 Local loop activated
Activation Indication Loop 2 AIL2 1110 Remote loop activated
Deactivation Confirmation DC 1111 Line- and if MODE1.CFS = ’1’ also lOM-
interface are powered down
Data Sheet
75
2001-03-07