PSB21391 Datasheet, PDF (100/253 Pages) Infineon Technologies AG – Siemens Codec with UPNTransceiver

PSB 21391
PSB 21393
HDLC Controller
RAM
RAM
EXMR.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo an receive pool full
interrupt ISTAH.RPF
is set.
HDLC
Receiver
32
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=11
8
4
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
an CMDR.RMC command.
Following CMDR.RMC
the 4 bytes of the
last block are
deleted.
HDLC
Receiver
EXMR.RFBS=01
RMC
µP
32
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=01
8
4
HDLC
Receiver
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTA)
is appended.
Meanwhile two
more short frames
have been
received.
RAM
RSTA
RSTA
RSTA
32
RFACC
RFIFO ACCESS
16 ^CONTROLLER
RFBS=01
8
FIFO.
RMC
µP
When the RFACC detects 16 valid bytes,
it sets an RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDR.RMC.
This causes the space occupied by the 16 bytes being
released.
Figure 50
RFIFO Operation
RAM
32
RFACC
HDLC
Receiver
RFIFO ACCESS
16 ^CONTROLLER
RSTA
RFBS=01
8
RSTA
RSTA
µP
After the RMC acknowledgement the
RFACC detects an RSTA byte, i.e. end of
the frame, therefore it asserts
an RME interupt and increments the
RBC counter by 2.
Data Sheet
90
2001-03-07