PSB21391 Datasheet, PDF (208/253 Pages) Infineon Technologies AG – Siemens Codec with UPNTransceiver

PSB 21391
PSB 21393
Detalled Register Description
TSS
... Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM-2 interface for the data channels.
7.2.3 CDAx_CR - Control Register Controller Data Access CH1x
Value after reset: See table below
7
0
CDAx_
0
0 EN_ EN_I1 EN_I0 EN_O1 EN_O0 SWAP
CR
TBM
RD/WR
(4E_H-4F_H)
Register
CDA1_CR
CDA2_CR
Value after Reset
00_H
00_H
Register Address
4E_H
4F_H
EN_TBM
... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
must be set to 08_H for monitoring from DU or 88_H for monitoring from DD respectively.
EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled
1: The input of the CDAx0, CDAx1 register is enabled
EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1
0: The output of the CDAx0, CDAx1 register is disabled
1: The output of the CDAx0, CDAx1 register is enabled
SWAP
... Swap Inputs
0: The time slot and data port for the input of the CDAxy register is defined by its own
TSDPxy register. The data port for the CDAxy input is vice versa to the output setting
for CDAxy.
1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of
CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data
port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port
for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition
for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to
CDAx0. The outputs are not affected by the SWAP bit.
Data Sheet
198
2001-03-07