TLF1963 Datasheet, PDF (8/24 Pages) Infineon Technologies AG – Low Dropout Linear Voltage Post Regulator

TLF1963
General Product Characteristics
4.2
Functional Range
Table 2 Functional Range
Pos. Parameter
Symbol Limit Values Unit Conditions
Min.
Max.
4.2.1 Input voltage
V_I
2.5
20
V
–
4.2.2 Output Capacitor’s Requirements C_Q
10
–
µF
–¹⁾
for Stability
ESR(C_Q) –
3
Ω
–²⁾
4.2.3 Junction temperature
T_j
-40
150
°C
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) relevant ESR value at f = 10 kHz
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3 Thermal Resistance
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
Package PG-TO263-5
4.3.1 Junction to Case¹⁾
4.3.2
4.3.3
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
0.84 –
19
–
64
–
K/W measured to heat
slug
K/W ²⁾
K/W footprint only³⁾
4.3.4
–
36
–
K/W 300 mm² heatsink
area³⁾
4.3.5
–
29
–
K/W 600 mm² heatsink
area³⁾
Package PG-TO252-5
4.3.6 Junction to Case¹⁾
4.3.7
4.3.8
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
0.78 –
24
–
95
–
K/W measured to heat
slug
K/W ²⁾
K/W footprint only³⁾
4.3.9
–
50
–
K/W 300 mm² heatsink
area³⁾
4.3.10
–
38
–
K/W 600 mm² heatsink
area³⁾
1) Not subject to production test, specified by design.
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70 µm Cu).
Data Sheet
8
Rev. 1.0, 2012-11-08