TLE6232GP_09 Datasheet, PDF (8/20 Pages) Infineon Technologies AG – Smart Six Channel Low-Side Switch

Data Sheet TLE 6232 GP
The effect of the integrated under-voltage detection is similar to the effect of an external reset
at pin Reset (except low current consumption):
- locks all power switches regardless of their input signals
- clears the fault registers
- resets SPI control register
Parallel Connection of Power Stages
The power stages which are connected in parallel have to be switched on and off simultane-
ously.
In case of overload the ground current and the power dissipation are increasing. The applica-
tion has to take into account that all maximum ratings are observed (e.g. operating tempera-
ture T_J and total ground current I_GND, see Maximal Ratings).
The maximum current limitation value (or overload detection threshold) of the parallel con-
nected power stages is the summation of the corresponding maximum values of the power
stages (IOUT_(lim)x + I_OUT(lim)y + ....).
Max. Nominal Current
Max. Clamping Energy On Resistance
2 power stages of the
same type
(see note 1)
3 power stages of the
same type
(see note 1,2)
2 power stages with the
same clamping voltage,
but different nominal
current (see note 3)
(I_max,OUTx+I_max,OUTy) x 0.9
(I_max,OUTx+I_max,OUTy+
I_max,OUTz) x 0.8
(I_max,OUTx+I_max,OUTy) x 0.8
Note 1: Power stages of the same type have the same nominal current
Note 2: Only for 3A power stages
Note 3: Parallel connection of power stage type 3A/53V with type 1.5A/53V
0.8 x (Ex + Ey)
0.5xR_{ON ,OUTx, y}
0.7 x (Ex + Ey + Ez)
Min (Eclpx , Eclpy)
0.34xR_{ON ,OUTx, y,z}
R xR _{ON ,OUTx ON ,OUTy}
R + R _{ON ,OUTx}
ON ,OUTy
SPI Interface
The serial SPI interface makes possible communication between TLE6232 and the microcon-
troller.
TLE 6232 GP always works in slave mode whereas the microcontroller provides the master
function. The maximum baud rate is 5MBaud.
Applying a chip select signal at CS and setting bit 7 and bit 6 of the instruction byte to „1“ and
„0“ TLE 6232 GP is selected by the SPI master. SI is the data input (Signal In), SO the data
output
(Signal Out). Via SCLK (Serial Clock Input) the SPI clock is given by the master.
V2.3
Page 8
2009-11-18