TLE42764_11 Datasheet, PDF (8/20 Pages) Infineon Technologies AG – Low Dropout Linear Voltage Regulator

TLE42764
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3 Thermal Resistance
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
TLE42764GV, TLE42764GV50 (PG-TO263-5)
4.3.1 Junction to Case¹⁾
R_thJC
–
4.3.2
4.3.3
Junction to Ambient¹⁾
R_thJA
–
–
3.6
–
22
–
74
–
K/W measured to heat
slug
K/W ²⁾
K/W footprint only³⁾
4.3.4
–
42
–
K/W 300 mm² heatsink
area³⁾
4.3.5
–
34
–
K/W 600 mm² heatsink
area³⁾
TLE42764DV, TLE42764DV50 (PG-TO252-5)
4.3.6 Junction to Case¹⁾
R_thJC
–
4.3.7
4.3.8
Junction to Ambient¹⁾
R_thJA
–
–
3.6
–
27
–
115 –
K/W measured to heat
slug
K/W ²⁾
K/W footprint only³⁾
4.3.9
–
52
–
K/W 300 mm² heatsink
area³⁾
4.3.10
–
40
–
K/W 600 mm² heatsink
area³⁾
TLE42764EV50 (PG-SSOP-14 exposed pad)
4.3.11
4.3.12
4.3.13
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
4.3.14
–
4.3.15
–
7
–
41
–
130 –
60
–
50
–
K/W –
K/W ²⁾
K/W footprint only³⁾
K/W 300 mm² heatsink
area on PCB³⁾
K/W 600 mm² heatsink
area on PCB³⁾
1) Not subject to production test, specified by design.
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
8
Rev. 1.2, 2011-02-15