1ED020I12FA Datasheet, PDF (8/22 Pages) Infineon Technologies AG – Single IGBT Driver IC

EICEDRIVER®
1ED020I12FA
3
Pin Configuration and Functionality
3.1
Pin Configuration
Pin Symbol
1 VEE2
2 VEE2
3 DESAT
4 GND2
5 NC
6 VCC2
7 OUT
8 CLAMP
9 VEE2
10 VEE2
11 GND1
12 GND1
13 IN+
14 IN-
15 RDY
16 FLT
17 RST
18 VCC1
19 GND1
20 GND1
Function
Negative power supply output side
Negative power supply output side
Desaturation protection
Signal ground output side
Not connected
Positive power supply output side
Driver output
Miller clamping
Negative power supply output side
Negative power supply output side
Signal ground input side
Signal ground input side
Non inverted driver input
Inverted driver input
Ready output
Fault output
Reset input
Positive power supply input side
Signal ground input side
Signal ground input side
1 VEE2
2 VEE2
3 DESAT
4 GND2
5 NC
6 VCC2
7 OUT
8 CLAMP
9 VEE2
10 VEE2
GND1 20
GND1 19
VCC1 18
/RST 17
/FLT 16
RDY 15
IN- 14
IN+ 13
GND1 12
GND1 11
Figure 4: PG-DSO-20-55
3.2
Pin Functionality
GND1
Ground connection of the input side.
IN+ Non-inverting driver input
IN+ control signal for the driver output if IN- is set to low.
(The IGBT is on if IN+ = high and IN- = low)
A minimum pulse width is defined to make the IC robust
against glitches at IN+. An internal Pull-Down-Resistor
ensures IGBT Off-State.
IN- Inverting driver input
IN- control signal for driver output if IN+ is set to high.
(IGBT is on if IN- = low and IN+ = high)
A minimum pulse width is defined to make the IC robust
against glitches at IN-. An internal Pull-Up-Resistor ensures
IGBT Off-State.
/RST (Reset) input
Function 1: Enable/shutdown of the input chip. (The IGBT is
off if /RST = low). A minimum pulse width is defined to
make the IC robust against glitches at IN-.
Function 2: Resets the DESAT-FAULT-state of the chip if
/RST is low for a time T_RST.
An internal Pull-Up-Resistor is used to ensure FLT status
output.
/FLT (Fault output)
Open-drain output to report a desaturation error of the IGBT
(FLT is low if desaturation occurs)
RDY (Ready status)
Open-drain output to report the correct operation of the
device. (RDY = high if both chips are above the UVLO level
and the internal chip transmission is faultless)
VCC1
5V power supply of the input chip
VEE2
Negative power supply pins of the output chip. If no negative
supply voltage is available, both pins have to be connected to
GND2.
Datasheet
8
Version 2.1, 2009-11-24