C161PI Datasheet, PDF (77/82 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

&3,
AC Characteristics
CLKOUT and READY (Reduced Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min. max.
min.
max.
CLKOUT cycle time
W₂₉ CC 40
40
2TCL
2TCL
ns
CLKOUT high time
W₃₀ CC 15
–
TCL – 10 –
ns
CLKOUT low time
W₃₁ CC 13
–
TCL – 12 –
ns
CLKOUT rise time
W₃₂ CC –
12
–
12
ns
CLKOUT fall time
W₃₃ CC –
8
–
8
ns
CLKOUT rising edge to W₃₄ CC 0 + W_A 8 + W_A 0 + W_A
8 + W_A
ns
ALE falling edge
Synchronous READY
W₃₅ SR 18
–
18
–
ns
setup time to CLKOUT
Synchronous READY
W₃₆ SR 4
–
4
–
ns
hold time after CLKOUT
Asynchronous READY W₃₇ SR 68
–
2TCL + W₅₈ –
ns
low time
Asynchronous READY W₅₈ SR 18
–
18
–
ns
setup time ¹⁾
Asynchronous READY W₅₉ SR 4
–
4
–
ns
hold time ¹⁾
Async. READY hold time W₆₀ SR 0
after RD, WR high
(Demultiplexed Bus) ²⁾
0
0
+ 2W_A +
W_C + W_F ²⁾
TCL - 25 ns
+ 2W_A + W_C
+ W_F ²⁾
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2W_A and W_C refer to the next following bus cycle, W_F refers to the current bus cycle.
The maximum limit for W₆₀ must be fulfilled if the next following bus cycle is READY controlled.
Data Sheet
75
1999-07