C161PI Datasheet, PDF (50/82 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

&3,
Direct Drive
When pins P0.15-13 (P0H.7-5) equal 011_B during reset the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of I_CPU directly follows the frequency of I_OSC so the high and low time of
I_CPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
I_OSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCL_min = 1/I_OSC * DC_min
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of I_OSC is compensated
so the duration of 2TCL is always 1/I_OSC. The minimum value TCL_min therefore has to be
used only once for timings that require an odd number of TCLs (1,3,...). Timings that
require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/I_OSC.
Note: The address float timings in Multiplexed bus mode (W₁₁ and W₄₅) use the maximum
duration of TCL (TCL_max = 1/I_OSC * DC_max) instead of TCL_min.
Data Sheet
48
1999-07