C161PI Datasheet, PDF (48/82 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

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Table 8
C161PI Clock Generation Modes
P0.15-13 CPU Frequency External Clock
(P0H.7-5) I_CPU = I_OSC * F Input Range ¹⁾
Notes
111
I_OSC * 4
2.5 to 6.25 MHz Default configuration
110
I_OSC * 3
3.33 to 8.33 MHz
101
I_OSC * 2
5 to 12.5 MHz
100
I_OSC * 5
2 to 5 MHz
011
I_OSC * 1
1 to 25 MHz
Direct drive ²⁾
010
I_OSC * 1.5
6.66 to 16.6 MHz
001
I_OSC / 2
2 to 50 MHz
CPU clock via prescaler
000
I_OSC * 2.5
4 to 10 MHz
1) The external clock input range refers to a CPU clock range of 10...25 MHz.
2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal 001_B during reset the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of I_CPU is half the frequency of I_OSC and the high and low time of I_CPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock I_OSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of I_OSC for any TCL.
Phase Locked Loop
For all combinations of pins P0.15-13 (P0H.7-5) except for 001_B and 011_B the on-chip
phase locked loop is enabled and provides the CPU clock (see table above). The PLL
multiplies the input frequency by the factor F which is selected via the combination of
pins P0.15-13 (i.e. I_CPU = I_OSC * F). With every F’th transition of I_OSC the PLL circuit
synchronizes the CPU clock to the input clock. This synchronization is done smoothly,
i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of I_CPU is constantly adjusted so
it is locked to I_OSC. The slight variation causes a jitter of I_CPU which also effects the
duration of individual TCLs.
Data Sheet
46
1999-07