SAL-XC866 Datasheet, PDF (72/113 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

SAL-XC866
Functional Description
3.11.1 Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes
divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud
rates based on its input clock f_PCLK, see Figure 28.
Fractional Divider
FDSTEP
1
FDM
10
FDEN&FDM
8-Bit Reload Value
Adder
FDEN
f_{PCLK Prescaler} f_{DIV clk}
FDRES
f_DIV
00
01
f_MOD
0
(overflow)
11
10
11
10
01
‘0’
00
0
1
8-Bit Baud Rate Timer ^fBR
R
NDOV
Figure 28 Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (f_MOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (f_DIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (f_BR) value is dependent on the following parameters:
• Input clock f_PCLK
• Prescaling factor (2^BRPRE) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
Data Sheet
68
V1.1, 2012-12