C164CI_02 Datasheet, PDF (71/484 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CI/C164SI
Derivatives
Central Processing Unit (CPU)
System Configuration Register SYSCON
This bit-addressable register provides general system configuration and control
functions. The reset value for register SYSCON depends on the state of the PORT0 pins
during reset (see hardware effectable bits).
SYSCON
System Control Register
SFR (FF12_H/89_H)
Reset Value: 0XX0_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKSZ
rw
ROM SGT ROM BYT CLK WR CS
S1 DIS EN DIS EN CFG CFG
-
OWD
DIS
BD
RST
EN
XPEN
VISI-
BLE
-
rw rw rwh rwh rw rwh rw - rwh rw rw rw -
Bit
VISIBLE
XPEN
BDRSTEN
OWDDIS
CSCFG
WRCFG
Function
Visible Mode Control
0: Accesses to XBUS peripherals are done internally
1: XBUS peripheral accesses are made visible on the external pins
XBUS Peripheral Enable Bit
0: Accesses to the on-chip X-Peripherals and their functions are
disabled
1: The on-chip X-Peripherals are enabled and can be accessed
Bidirectional Reset Enable Bit
0: Pin RSTIN is an input only
1: Pin RSTIN is pulled low during the internal reset sequence
after any reset
Oscillator Watchdog Disable Bit
0: The on-chip oscillator watchdog is enabled and active
1: The on-chip oscillator watchdog is disabled and the CPU clock is
always fed from the oscillator input
Chip Select Configuration Control
0: Latched CS mode. The CS signals are latched internally
and driven to the (enabled) port pins synchronously
1: Unlatched CS mode. The CS signals are derived directly from
the address and driven to the (enabled) port pins
Write Configuration Control (Set according to pin P0H.0 during reset)
0: Pins WR and BHE retain their normal function
1: Pin WR acts as WRL, pin BHE acts as WRH
User’s Manual
4-13
V3.1, 2002-02