C164CI_02 Datasheet, PDF (389/484 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CI/C164SI
Derivatives
System Reset
20.1
Reset Sources
Several external or internal sources can generate a reset for the C164CI. Software can
identify the respective reset source via the reset source indication flags in register
WDTCON. Generally, any reset causes the same actions on the C164CI’s modules. The
differences are described in the following sections.
Hardware Reset
A hardware reset is triggered when the reset input signal RSTIN is latched low. To
ensure the recognition of the RSTIN signal (latching), it must be held low for at least
100 ns plus 2 CPU clock cycles (input filter plus synchronization). Shorter RSTIN pulses
may also trigger a hardware reset if they coincide with the latch’s sample point. The
actual minimum duration for a reset pulse depends on the current CPU clock generation
mode. The worst case is generating the CPU clock via the SlowDown Divider using the
maximum factor while the configured basic mode uses the prescaler (f_CPU = f_OSC / 64 in
this case).
After the reset sequence has been completed, the RSTIN input is sampled again. If the
reset input signal is inactive at that time, the internal reset condition is terminated
(indicated as short hardware reset, SHWR). If the reset input signal is still active at that
time, the internal reset condition is prolonged until RSTIN becomes inactive (indicated
as long hardware reset, LHWR).
During a hardware reset, the inputs for the reset configuration (PORT0, RD, ALE) need
some time to settle on the required levels, especially if the hardware reset aborts a read
operation from an external peripheral. During this settling time, the configuration may
intermittently be wrong. For the duration of one internal reset sequence after a reset has
been recognized, the configuration latches are not transparent; thus the (new)
configuration becomes valid earliest after the completion of one reset sequence. This
usually covers the required settling time.
When the basic clock is generated by the PLL, the internal reset condition is
automatically extended until the on-chip PLL has locked.
The input RSTIN provides an internal pull-up device equalling a resistor of 50 kΩ to
250 kΩ (the minimum reset time must be determined by the lowest value). Simply
connecting an external capacitor is sufficient for an automatic power-on reset (see b) in
Figure 20-1). RSTIN may also be connected to the output of other logic gates (see a) in
Figure 20-1). See also “Bidirectional Reset” on Page 22-4 in this case.
Note: A power-on reset requires an active time of two reset sequences (1036 CPU clock
cycles) after a stable clock signal is available (about 10 … 50 ms, depending on
the oscillator frequency, to allow the on-chip oscillator to stabilize).
User’s Manual
20-2
V3.1, 2002-02