TLF80511EJ_15 Datasheet, PDF (7/20 Pages) Infineon Technologies AG – Low Dropout Linear Fixed Voltage Regulator

4.2
Functional Range
TLF80511EJ
General Product Characteristics
Table 2 Functional Range
Parameter
Symbol
Values
Unit Note / Test Condition Number
Min.
Typ. Max.
Input Voltage Range for Normal
Operation
Extended Input Voltage Range
Output Capacitor’s
Requirements for Stability
Output Capacitor’s
Requirements for Stability
V_I
V_Q,nom + V_dr –
V_I,ext
3.3
–
C_Q
1
–
ESR(C_Q) –
–
40 V –
40
V
T_j > 25 °C ¹⁾
–
µF –²⁾
5
Ω
–³⁾
Junction Temperature
T_j
-40
–
150 °C –
1) Between min. value and V_Q,nom + V_dr: V_Q = V_I - V_dr. Below min. value: V_Q = 0 V
2) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
3) relevant ESR value at f = 10 kHz
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3 Thermal Resistance
Parameter
Symbol
Values
Unit Note / Test Condition Number
Min. Typ. Max.
Package Version PG-DSO8-EP
Junction to Case¹⁾
Junction to Ambient¹⁾
Junction to Ambient¹⁾
Junction to Ambient¹⁾
R_thJC
–
11
–
K/W –
R_thJA
–
41
–
K/W ²⁾
R_thJA
–
152 –
K/W footprint only³⁾
R_thJA
–
67
–
K/W 300 mm² heatsink
area on PCB³⁾
Junction to Ambient¹⁾
R_thJA
–
56
–
K/W 600 mm² heatsink
area on PCB³⁾
1) Not subject to production test, specified by design
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
7
Rev. 1.0, 2014-11-17