TLF80511EJ_15 Datasheet, PDF (5/20 Pages) Infineon Technologies AG – Low Dropout Linear Fixed Voltage Regulator

3
Pin Configuration
3.1
Pin Assignment PG-DSO8-EP
TLF80511EJ
Pin Configuration
I
1
GND
2
8
n.c.
7
n.c.
n.c.
3
6
n.c.
Q
4
5
Figure 2 Pin Configuration
3.2
Pin Definitions and Functions PG-DSO8-EP
n.c.
Pin
Symbol
1
I
2
GND
3
n.c.
4
Q
5, 6, 7, 8 n.c.
Pad
-
Function
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
Ground
Not connected
Leave open or connect to GND
Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 7
Not connected
Leave open or connect to GND
Exposed Pad
Connect to heatsink area;
Connect with GND on PCB
Data Sheet
5
Rev. 1.0, 2014-11-17