HDSP2110S Datasheet, PDF (7/13 Pages) Infineon Technologies AG – 8-Character 5x7 Dot Matrix Parallel Input Alphanumeric Intelligent Display

Figure 7. Block Diagram
OSC
÷32
Counter
÷7
Counter
Row
Drivers
÷128
Counter
8 Digit Display
Column
Drivers
÷3
Counter
Character
RAM
Decode
Character
RAM
D Latch
Holding
Register
ROM ₆₄
Word
Decode
ROM
Data Bus
Character
Decode ₁₆
for Display
UDC
16 ^RAM
4 ^UDC
4 ^Character
Address
Decode
Register
(Read/Write)
Column
Latch
MS
a
l
s
a
5
t
e
25
v
e
r
5
Self
Test
25
Cursor
Controls
and
Display
MUX
Control
Word
Register
Flash
RAM
Functional Description
The display's user interface is organized into five memory
areas. They are accessed using the Flash Input, FL, and
address lines, A3 and A4. All the listed RAMs and Registers
may be read or written through the data bus. See Table 1. Each
input pin is described in Pin Definitions.
Five Basic Memory Areas
Character RAM
Stores either ASCII (Katakana)
character data or an UDC RAM
address
Flash RAM
1 x 8 RAM which stores Flash data
User-Defined
Character RAM
(UDC RAM)
Stores dot pattern for custom
characters
User-Defined Address
Register (UDC
Address Register)
Provides address to UDC RAM
when user is writing or reading
custom character
Control Word
Register
Enables adjustment of display
brightness, flash individual charac-
ters, blink, self test or clearing
the display
RST can be used to initialize display operation upon power up
or during normal operation. When activated, RST will clear the
Flash RAM and Control Word Register (00H) and reset the
internal counter. All eight display memory locations will be set
to 20H to show blanks in all digits.
FL pin enables access to the Flash RAM. The Flash RAM will
set (D0=1) or reset (D0=0) flashing of the character addressed
by A0–A2.
The 1 x 8 bit Control Word Register is loaded with attribute
data if A3=0.
The Control Word Logic decodes attribute data for proper
implementation.
Character ROM is designed for 128 ASCII characters. The
ROM is Mask Programmable for custom fonts.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0)
could be an input from another HDSP211X display for the syn-
chronization of blinking for multiple displays.
The Display Multiplexer controls the Row Drivers so no addi-
tional logic is required for a display system.
The Display has eight digits. Each digit has 35 LEDs clustered
into a 5 x 7 dot matrix.
 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • [phone]
7
HDSP2110S/1S/2S/3S/4S/5S
March 24, 2000-13