1ED020I12FA2 Datasheet, PDF (7/27 Pages) Infineon Technologies AG – Single IGBT Driver IC

1ED020I12FA2
Single IGBT Driver IC
Pin Configuration and Functionality
1 ^VEE2
2 ^VEE2
3 ^DESAT
4 GND2
5 NC
6 VCC2
7 OUT
8 ^CLAMP
9 ^VEE2
10 ^VEE2
Figure 2 PG-DSO-20 (top view)
3.2
Pin Functionality
GND1 ₂₀
GND1 ₁₉
VCC1 ₁₈
/RST 17
/FLT 16
RDY 15
IN- 14
IN+ ₁₃
GND1 ₁₂
GND1 ₁₁
GND1
Ground connection of the input side.
IN+ Non Inverting Driver Input
IN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low)
A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor
ensures IGBT Off-State.
IN- Inverting Driver Input
IN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high)
A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor
ensures IGBT Off-State.
/RST Reset Input
Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is
defined to make the IC robust against glitches at /RST.
Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time T_RST. An internal Pull-Up-Resistor
is used to ensure /FLT status output.
/FLT Fault Output
Open-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs)
Data Sheet
7
Rev. 3.0
2016-04-04