PEB3456E Datasheet, PDF (66/424 Pages) Infineon Technologies AG – Channelized T3 Termination with DS3 Framer, M13 Multiplexer, T1/ E1 Framers and 256 Channel HDLC/PPP controller

PEB 3456 E
Functional Description
discarded and for each discarded frame a ’Silent Discard’ interrupt vector with the bits
HRAB and RAB set is generated.
If the current data section was filled and does contain the end of frame a ’Frame End’
interrupt vector is generated and the descriptor is updated on the FE bit and the C bit.
Therefore the status of this receive descriptor is error free. With the next request of the
receive buffer, the data management unit repolls the HOLD bit of the current receive
descriptor. If the hold bit is removed, it branches to the next descriptor. If the HOLD bit
is still ’1’, an internal poll bit is set. As long as the HOLD bit remains set, further data of
the same channel is discarded and for each discarded frame a ’Silent Discard’ interrupt
vector with bits HRAB and RAB set is generated.
When the receive buffer request matches exactly the remaining size of the data section
and the data block does not contain the end of a packet, it is stored completely in the
data section. The descriptor is updated immediately (C bit set). With the next receive
buffer request, the data management unit repolls the HOLD bit of the current receive
descriptor. If the HOLD bit is removed, it branches to the next descriptor. If the HOLD Bit
is still ’1’, an internal poll bit is set. Additionally a ’Hold Caused Receive Abort’ interrupt
vector is generated and the rest of the frame is discarded. As long as the HOLD bit
remains set further data of the same channel is discarded and for each discarded frame
a ’Silent Discard’ interrupt vector is generated.
The system CPU can remove the hold condition, when the next receive descriptor is
available in shared memory. Therefore the CPU has to execute a ‘Receive Hold Reset’
command, which will reactivate the channel. When the receive buffer requests a new
data transfer, the data management unit will repoll the last receive descriptor. If the
HOLD bit was removed, the data management unit branches to the next receive
descriptor pointed to by bit field NextReceiveDescriptor.
Note: In protocol modes HDLC and PPP data from receive buffer is discarded until the
end of a received frame is reached. As soon as the beginning of a new frame is
received, the data management unit starts to fill the data section.
Note: In transparent mode data transferred from receive buffer is written immediately to
the data section of the next receive descriptor.
If the CPU issues a ’Receive Hold Reset’ command and does not remove the HOLD bit
(erroneous programming), no action will take place.
4.3.4 Transmit Descriptor
The transmit descriptor in shared memory is initialized by the host CPU and is read
afterwards by the TE3-CHATT. The address pointer to the first transmit descriptor is
stored in the on-chip channel database, when requested to do so by the host CPU via
the ’Transmit Init’ command. The first three DWORDs of a transmit descriptor are read
when the transmit buffer requests a data transfer for this channel and then they are
stored in the on-chip memory. Also they are read when branching from one transmit
Data Sheet
66
05.2001