TC1165 Datasheet, PDF (65/133 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

Preliminary
TC1165/TC1166
Functional Description
Clock
f_{ML I0}
Control
Address
Decoder
Interrupt
Control
SR[3:0]
MLI 0
Module
(Kernel )
SR[4:7]
To DMA
BRKOUT
Cerberus
TCLK
TREADYA
TREADYB
TREADYD
TVALIDA
TVALIDB
TVALIDD
TDATA
RCLKA
RCLKB
RCLKD
RREADYA
RREADYB
RREADYD
RVALIDA
RVALIDB
RVALIDD
RDATAA
RDATAB
RDATAD
Port 2
Control
Port 5
Control
P2.0 / TCLK 0
P2.1 / TREADY0A
P2.2 / TVALID0A
P2.3 / TDATA0
P2.4 / RCLK 0A
P2.5 / RREADY0A
P2.6 / RVALID0A
P2.7 / RDATA0A
P5.15 / TCLK0
P5.14 / TREADY0B
P5.13 / TVALID0B
P5.12 / TDATA0
P5.11 / RCLK0B
P5.10 / RREADY0B
P5.9 / RVALID0B
P5.8 / RDATA0B
Clock
f_{ML I1}
Control
Address
Decoder
Interrupt
Control
SR[1:0]
MLI1
Module
( Kernel )
N.C.
To DMA
SR[3:2]
SR[4:7]
BRKOUT
Cerberus
TCLK
TREADYA
TREADYD
TVALIDA
TVALIDD
TDATA
RCLKA
RCLKD
RREADYA
RREADYD
RVALIDA
RVALIDD
RDATAA
RDATAD
Port 5
Control
Figure 3-9 Block Diagram of the MLI Modules
Data Sheet
61
P5.11 / TCLK1
P5.10 / TREADY1
P5.9 / TVALID1
P5.8 / TDATA1
P5.15 / RCLK1
P5.14 / RREADY1
P5.13 / RVALID1
P5.12 / RDATA1
MCB06322_MCB06323
V1.0, 2008-04