TC1165 Datasheet, PDF (127/133 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1165/TC1166
Preliminary
Electrical Parameters
4.3.8.2 Micro Second Channel (MSC) Interface Timing
Table 4-18 provides the characteristics of the MSC timing in the TC1165/TC1166.
Table 4-18 MSC Interface Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Limit Values
Unit
FCLP clock period¹⁾²⁾
SOP/ENx outputs delay from FCLP
Min.
Max.
t₄₀
CC 2 × T_MSC3) –
ns
t₄₅ CC -10
10
ns
SDI bit time
t₄₆
SR 8 × T_MSC –
ns
SDI rise time
t₄₈
SR
100
ns
SDI fall time
t₄₉
SR
100
ns
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × T_MSC.
3) T_MSCmin = T_SYS = 1/f_SYS. When f_SYS = 80MHz, t₄₀ = 25ns
t₄₀
FCLP
t₄₅
t₄₅
SOP
EN
0.9 V_DDP
0.1 V_DDP
SDI
t₄₈
t₄₉
0.9 V_DDP
0.1 V_DDP
t₄₆
t₄₆
MS C_Tmg_1.v s d
Figure 4-18 MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
123
V1.0, 2008-04