TC1165 Datasheet, PDF (57/133 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1165/TC1166
Preliminary
Functional Description
3.9
High-Speed Synchronous Serial Interfaces (SSC0 and SSC1)
Figure 3-5 shows a global view of the functional blocks and interfaces of the two high-
speed Synchronous Serial Interfaces, SSC0 and SSC1.
Clock
Control
f_{SSC 0}
f_{C LC0}
Address
Decoder
EIR
Interrupt TIR
Control RIR
To
DMA
SSC0_RDR
SSC0_TDR
M/S Select ¹⁾
Enable ¹⁾
SSC0
Module
(K ernel )
Master
Slave
Slave
Master
Slave
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
SCLKA
SCLKB
SCLK
SLSI1
SLSI[7:2] ¹⁾
SLSO[2:0]
Port 3
Control
Master
SLSO[5:3]
SLSO6
SLSO7 ¹⁾
A2 P3.4 /MTSR0
A2 P3.3 /MRST0
A2 P3.2 /SCLK0
A2 P3.7 /SLSI0
P3.5 /SLSO00 /
A2 SLSO10 / SLSO00
AND SLSO10
A2 ^{P3.6 /SLSO01 /}
SLSO11 / SLSO01
AND SLSO11
A2
P3.7 /SLSO02 /
SLSO12
A2 P3.8 /SLSO06
Clock
Control
fSSC 1
fC LC1
Address
Decoder
EIR
Interrupt TIR
Control RIR
SSC1_RDR
To
DMA ^SSC1_TDR
SSC1
Module
(K ernel )
SLSO[2:0]
Master
SLSO[5:3]
SLSO6 ¹⁾
SLSO7
SLSI1
Slave _SLSI[7:2] ¹⁾
Master
MRSTA
MRSTB
MTSR
Slave
MTSRA
MTSRB
MRST
Port 2
Control
M/S Select ¹⁾
Enable ¹⁾
1) These lines are not connected
Slave
Master
SCLKA
SCLKB
SCLK
Port 1
Control
Figure 3-5 Block Diagram of the SSC Interfaces
Data Sheet
53
A2
P2.1 /SLSO03 /
SLSO13
A2
P2.8 /SLSO04 /
SLSO14
A2 ^{P2.9 /SLSO05 /}
SLSO15
A1 P2.13 /SLSI1
A2 P2.12 /MTSR1A
A2 P2.10 /MRST1A
A2 P2.11 /SCLK1A
A2 P1.10 /SLSO17
A2 P1.8 /MTSR1B
A2 P1.9 /MRST1B
A2 P1.11 /SCLK1B
MCB06225_c
V1.0, 2008-04