TLE6244X Datasheet, PDF (61/70 Pages) Infineon Technologies AG – 18 Channel Smart Lowside Switch

TLE 6244X
3.10 µsec-bus
FCL/IN16
FDA/IN6
SSY/IN7
tcyc
tsetup thold
tshold
tSF
tswitch
Timing µsec-bus
Notes for the timing:
Timing definitions are starting or ending at a voltage level of 1V (Low Level) resp. 2V (High Level).
During SSY = high the clock at FCL may be interrupted, i.e. there is no need for a clock during SSY = high.
The clock signal may remain on high or low statically during SSY = high.
A rising edge at SSY and a falling edge at FCL must not occur simultaneously!
On the rising edge of SSY the 16 bits clocked in TLE6244X by the last 16 falling edges at FCL are latched.
3.10.1 Input FCL,
FDA, SSY
µsec-bus interface pins
3.10.1.1 Low Level
3.10.1.2 High Level
3.10.1.3 Hysteresis
3.10.1.4 Input Ca-
pacity
3.10.1.5 Input Cur-
rent
Pull up current source connected
to VDD
3.10.2 Timing
Cycle Time
Data setup time
Data hold time
Switching time on FCL
fFCL < 10MHz
B
U_FCLl
U_FDAl
U_SSYl
1.0
V
B
U_FCLh 2.0
V
U_FDAh
U_SSYh
C
∆U_{FCL 0.1}
∆U_FDA
∆U_SSY
0.6 V
C
C_FCL
C_FDA
C_SSY
10 pF
A
I_FCL
5
10 20 µA
I_FDA
I_SSY
C tCYC 62
nsec
C tsetup 10
nsec
C
t_hold
10
nsec
C
t_switch
30 nsec
Final Data Sheet
61
V4.2, 2003-08-29