V23814-K1306-M136 Datasheet, PDF (6/27 Pages) Infineon Technologies AG – PAROLI Tx AC, 1.25 Gbit/s

V23814-K1306-M136
V23815-K1306-M136
Pin Configuration
Pin Description Receiver
Pin Symbol Level/ Logic Description
No.
1
V_EE
2
V_CC
Ground
Power supply voltage of preamplifier
and analog circuitry
3
V_CC
Power supply voltage of preamplifier
and analog circuitry
4
t.b.l.o.
to be left open
5
OEN LVCMOS In Output Enable
High = normal operation
Low = sets all Data Outputs to low
This input has an internal pull-up which pulls to high
level when this input is left open
6
SD1
LVCMOS Out Signal Detect on fiber #1.
High = signal of sufficient AC power is
present on fiber #1
Low = signal on fiber #1 is insufficient.
7
V_CCO
8
V_EE
9
t.b.l.o.
Power supply voltage of output stages
Ground
to be left open
10
V_EE
Ground
11
V_EE
Ground
12
V_EE
Ground
13 DO01P LVDS Out Data Output #1, non-inverted
14 DO01N LVDS Out Data Output #1, inverted
15
V_EE
Ground
16
V_EE
Ground
17 DO02P LVDS Out Data Output #2, non-inverted
18 DO02N LVDS Out Data Output #2, inverted
19
V_EE
Ground
20
V_EE
Ground
21 DO03P LVDS Out Data Output #3, non-inverted
22 DO03N LVDS Out Data Output #3, inverted
23
V_EE
24
V_EE
25 t.b.l.o.
Ground
Ground
to be left open
Data Sheet
6
2001-12-01