XC164N-16F Datasheet, PDF (57/73 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

4.3
AC Parameters
XC164N
Derivatives
Electrical Parameters
4.3.1 Definition of Internal Timing
The internal operation of the XC164N is controlled by the internal master clock f_MC.
The master clock signal f_MC can be generated from the oscillator clock signal f_OSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate f_MC.
This influence must be regarded when calculating the timings for the XC164N.
Phase Locked Loop Operation (1:N)
f _OSC
f_MC
Direct Clock Drive (1:1)
f _OSC
f_MC
Prescaler Operation (N:1)
f _OSC
f_MC
TCM
TCM
TCM
MCT05555
Figure 13 Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 13 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
Data Sheet
55
V1.2, 2006-08