PEB4266T-V1.2 Datasheet, PDF (50/374 Pages) Infineon Technologies AG – Dual Channel Subscriber Line Interface Concept

DuSLIC
Functional Description
2.5.5 Internal Balanced Ringing via SLICs
SLIC-E/-E2 and SLIC-P support internal balanced ringing up to V_RING,RMS = 85 Vrms,
while SLIC-S supports balanced ringing up to V_RING,RMS = 45 Vrms¹⁾.
The ringing signal is generated digitally within the SLICOFI-2x.
V_DROP,T
V_HR
v_T
V_Tp
V_RING,pp= V_Tp - V_Rp
BGND
V_DC,RING
V_DROP,R
V_Rp
v_R
V_BATH
V_BATR
Figure 24
SLIC-E
SLIC-E2 SLIC-P
SLIC-S
Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P
ezm140315
In ringing mode, the DC feeding regulation loop is not active. A programmable DC ring
offset voltage is applied to the line instead. During ring bursts, the ringing DC offset and
the ringing signal are summed digitally within SLICOFI-2x in accordance with the
programmed values. This signal is then converted to an analog signal and is applied to
the SLIC. The SLIC amplifies the signal and supplies the line with ringing voltages up to
85 Vrms. In balanced ringing mode, the SLIC uses an additional supply voltage V_HR for
SLIC-E/-E2/-S and V_BATR for SLIC-P. The total supply span is now V_HR – V_BATH for
SLIC-E/-E2/-S and V_BATR for SLIC-P.
The maximum ringing voltage that can be achieved is:
for SLIC-E/-E2/-S:
for SLIC-P:
where:
V_RING,RMS = (V_HR – V_BATH – V_DROP,TR – V_DC,RING)/1.41
V_RING,RMS = (–V_BATR – V_DROP,TR – V_DC,RING)/1.41
V_DROP,TR = V_DROP,T + V_DROP,R
1) In this case V_RING,RMS = V_TR,RMS = V_TR0,RMS because of the low impedance of the SLIC output (< 1 Ω). V_TR,RMS is
the open-circuit rms voltage measured directly at pins RING and TIP at the SLIC output with ringer load.
V_TR0,RMS is the rms voltage measured directly at pins RING and TIP at the SLIC output without any ringer load.
For calculation of the ringing voltage at the ringer load, see the Application Note DuSLIC Voltage and Power
Dissipation Calculation and its accompanying MS Excel Sheet for calculation.
Preliminary Data Sheet
50
DS3, 2003-07-11