PEB4266T-V1.2 Datasheet, PDF (304/374 Pages) Infineon Technologies AG – Dual Channel Subscriber Line Interface Concept

DuSLIC
1F_H OFR1
Offset Register 1 (High Byte)
00_H
Y
Bit
7
6
5
4
3
2
1
0
OFFSET-H[7:0]
OFFSET-H[7:0] Offset register High Byte.
20_H OFR2
Offset Register 2 (Low Byte)
00_H
Bit 7
6
5
4
3
2
1
OFFSET-L[7:0]
Y
0
OFFSET-L[7:0]
Offset register Low Byte.
The value of this register together with OFFSET-H is added to the
input of the DC loop to compensate a given offset of the current
sensors in the SLIC-S/-S2.
Preliminary Data Sheet
304
DS3, 2003-07-11