PEB4266T-V1.2 Datasheet, PDF (100/374 Pages) Infineon Technologies AG – Dual Channel Subscriber Line Interface Concept

DuSLIC
Operational Description
3.8.2.5 DC Level Metering
The path of the DC level meter is shown in Figure 40. Hereby, the DC level meter results
will be determined and prepared depending on certain configuration settings. The
selected input signal becomes digitized after pre-filtering and analog-to-digital
conversion. The DC level meter is selected and enabled as shown in Table 19:
Table 19 Selecting DC Level Meter Path
LM-SEL[3:0] in
register LMCR2
DC Level Meter Path
0100
DC out voltage on DCP-DCN
0101
DC current on IT
1001
DC current on IL
1010
Voltage on IO3
1011
Voltage on IO4
1101
1110
V_DD
Offset of DC-pre-filter (short circuit on DC-pre-filter input)
1111
Voltage on IO4 – IO3
The effective sampling rate after the decimation stages is 2 kHz. The decimated value
has a resolution of 19 bits. The offset compensation value (see Chapter 3.8.2.8) within
the offset registers OFR1 (bits OFFSET-H[7:0]) and OFR2 (bits OFFSET-L[7:0]) can be
set to eliminate the offset caused by the SLIC current sensor, pre-filter, and analog-to-
digital converter. After the summation point the signal passes a programmable digital
gain filter. The additional gain factor is either 1 or 16 depending on register LMCR1 (bit
DC-AD16):
• LMCR1 (bit DC-AD16) = 0: No additional gain factor
• LMCR1 (bit DC-AD16) = 1: Additional gain factor of 16
The rectifier after the gain filter can be turned on/off with:
• LMCR2 (bit LM-RECT) = 0: Rectifier disabled
• LMCR2 (bit LM-RECT) = 1: Rectifier enabled
A shift-factor K_INTDC in front of the integrator prevents the level meter during an
integration operation to create an overflow. If an overflow in the level meter occurs, the
output result will be ± full scale (see Table 18).
If the shift factor K_INTDC is set to e.g. 1/8, the content of the level meter result register is
the integration result divided by 8.
Preliminary Data Sheet
100
DS3, 2003-07-11