ICB1FL02G Datasheet, PDF (5/37 Pages) Infineon Technologies AG – Smart Ballast Control IC for Fluorescent Lamp Ballasts

ICB1FL02G
Pin Configuration and Description
1 Pin Configuration and Description
1.1 Pin Configuration PG-DSO-18-1 1.2 Pin Description
Pin Symbol Function
1 LSCS Low side current sense (inverter)
2 LSGD Low side gate drive (inverter)
3 VCC
Supply voltage
4 GND
Controller ground
5 PFCGD PFC gate drive
6 PFCCS PFC current sense
7 PFCZCD PFC zero current detector
8 PFCVS PFC voltage sense
9 RFRUN Set R for run frequency
10 RFPH Set R for preheating frequency
11 RTPH Set R for preheating time
12 RES
Restart after lamp removal
13 LVS1 Lamp voltage sense 1
14 LVS2 Lamp voltage sense 2
15 n.e.
Not existing
16 n.e.
Not existing
17 HSGND High side ground
18 HSVCC High side supply voltage
19 HSGD High side gate drive
20 HSGND High side ground
LSCS (Low side current sense, Pin 1)
This pin is directly connected to the shunt resistor
which is located between the Source terminal of the
low-side MOSFET of the inverter and ground.
Internal clamping structures and filtering measures
allow for sensing the Source current of the low-side
inverter MOSFET without additional filter components.
There is a first threshold of 0,8V, which provides a
couple of increasing steps of frequency during ignition
mode, if exceeded by the sensed current signal for a
time longer than 250ns. If the sensed current signal
exceeds a second threshold of 1,6V for longer than
400ns during all operating modes, a latched shut down
of the IC will be the result.
LSGD (Low side gate drive, Pin 2)
The Gate of the low-side MOSFET in a half-bridge
inverter topology is controlled by this pin. There is an
active L-level during UVLO (undervoltage lockout) and
a limitation of the max. H-level at 11V during normal
operation. Turning on the MOSFET softly (with reduced
di_DRAIN/dt), the Gate drive voltage rises within 220ns
from L-level to H-level. The fall time of the Gate drive
voltage is less than 50ns in order to turn off quickly.
This measure produces different switching speeds
during turn-on and turn-off as it is usually achieved with
a diode in parallel to a resistor in the Gate drive loop. It
is recommended to use a resistor of about 15Ohm
between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor. The
dead time between LSGD signal and HSGD signal is
1800ns typically.
LSCS
LSGD
VCC
GND
PFCGD
PFCCS
PFCZCD
PFCVS
RFRUN
RFPH
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PG-DSO-18-1 (300mil)
HSGND
HSGD
HSVCC
HSGND
LVS2
LVS1
RES
RTPH
VCC (Supply voltage, Pin 3)
This pin provides the power supply of the ground
related section of the IC. There is a turn-on threshold at
14V and an UVLO threshold at 10,5V. Upper supply
voltage level is 17,5V. There is an internal zener diode
clamping Vcc at 16V (2mA typically). The zener current
is internally limited to 5mA max. For higher current
levels an external zener diode is required. Current
consumption during UVLO and during fault mode is
less than 150µA. A ceramic capacitor close to the
supply and GND pin is required in order to act as a low-
impedance power source for Gate drive and logic
signal currents.
GND (Ground, Pin 4)
This pin is connected to ground and represents the
ground level of the IC for supply voltage, Gate drive
and sense signals.
Datasheet Version 1.2
5
February 2006