HYR163240G Datasheet, PDF (5/14 Pages) Infineon Technologies AG – Direct RDRAM RIMM Modules (with 288 Mbit RDRAMs)

HYR16xx40G / HYR18xx40G
Rambus RIMM Modules
Module Connector Pad Description
Signal
Module Connector Pads I/O
GND
A1, A3, A5, A7, A9, A11, –
A13, A15, A17, A19, A21,
A23, A25, A27, A29, A31,
A33, A39, A52, A60, A62,
A64, A66, A68, A70, A72,
A74, A76, A78, A80, A82,
A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11,
B13, B15, B17, B19, B21,
B23, B25, B27, B29, B31,
B33, B39, B52, B60, B62,
B64, B66, B68, B70, B72,
B74, B76, B78, B80, B82,
B84, B86, B88, B90, B92
LCFM
B10
I
LCFMN
B12
I
LCMD
B34
I
LCOL4 …
LCOL0
A20, B20, A22, B22, A24 I
LCTM
A14
I
LCTMN
A12
I
LDQA8 … A2, B2, A4, B4, A6, B6, I/O
LDQA0
A8, B8, A10
Type
–
Description
Ground reference for RDRAM core
and interface. 72 PCB connector
pads.
RSL
RSL
V_CMOS
RSL
RSL
RSL
RSL
Clock from master. Interface clock
used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock
used for receiving RSL signals from
the Channel. Negative polarity.
Serial Command used to read from
and write to the control registers.
Also used for power management.
Column bus. 5-bit bus containing
control and address information for
column accesses.
Clock to master. Interface clock
used for transmitting RSL signals to
the Channel. Positive polarity.
Clock to master. Interface clock
used for transmitting RSL signals to
the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a
byte of read or write data between
the Channel and the RDRAM.
LDQA8 is non-functional on
modules with x16 RDRAM devices.
INFINEON Technologies
5
7.01