TLE7810G Datasheet, PDF (43/53 Pages) Infineon Technologies AG – Integrated double low-side switch, high-side/LED driver, hall supply, wake-up inputs and LIN communication with embedded MCU (16kB Flash)

TLE7810G
General Product Characteristics
Table 14 Electrical Characteristics (cont’d)
V_S = 13.5 V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
16.4.103 TxD dominant time out t_torec
recovery time
Min. Typ. Max.
–
10
–
μs
V_TxD = 5 V¹⁾
Transfer Rate 20 kbit/s; 1 μs < τ = R_L × C_bus < 5 μs
16.4.104 Duty cycle D1
D1
0.396 –
–
μs duty cycle 1:
TH_Rec(max) = 0.744 × V_S;
TH_Dom(max) = 0.581 × V_S;
V_S = 7.0 … 18 V;
t_bit = 50 μs;
D1 = t_{bus_rec(min)} / 2 t_bit;
(LIN Spec 2.0;
Line 3.3.1)
16.4.105 Duty cycle D2
D2
–
–
0.581 μs duty cycle 2:
TH_Rec(min) = 0.422 × V_S;
TH_Dom(min) = 0.284 × V_S;
V_S = 7.6 … 18 V;
t_bit = 50 μs;
D2 = t_{bus_rec(max)} / 2 t_bit;
(LIN Spec 2.0;
Line 3.3.2)
Transfer Rate 10.4 kbit/s; 1 μs < τ = R_L × C_bus < 5 μs
16.4.106 Duty cycle D3
D3
0.417 –
–
μs duty cycle 3:
TH_Rec(max) = 0.778 × V_S;
TH_Dom(max) = 0.616 × V_S;
V_S = 7.0 … 18 V;
t_bit = 96 μs;
D3 = t_{bus_rec(min)} / 2 t_bit;
(LIN Spec 2.0;
Line 3.4.1)
16.4.107 Duty cycle D4
SPI Data Input Timing¹⁾
D4
–
–
0.590 μs duty cycle 4:
TH_Rec(min) = 0.389 × V_S;
TH_Dom(min) = 0.251 × V_S;
V_S = 7.6 … 18 V;
t_bit = 96 μs;
D4 = t_{bus_rec(max)} / 2 t_bit;
(LIN Spec 2.0;
Line 3.4.2)
16.4.108
16.4.109
16.4.110
16.4.111
16.4.112
16.4.113
Clock period
Clock high time
Clock low time
Clock low before CSN low
CSN setup time
CLK setup time
t_pCLK
t_CLKH
t_CLKL
t_bef
t_lead
t_lag
250 –
–
ns –
125 –
–
ns –
125 –
–
ns –
125 –
–
ns –
250 –
–
ns –
250 –
–
ns –
Data Sheet
43
Rev. 3.01, 2008-04-15